i've always wondered, about the entire design. If Asics are procs then
they have registers. How much cache/mem would a lb's have per ASIC? Seek
times from the "shared memory" numbers. etc etc. What would be a good
source/list be to post these quries?
On Fri, 16 Feb 2001, tony bourke wrote:
> remember, ASICs are processors too, the only difference is that ASICs are
> designed with a single purpose in mind such as IP functions, rather than
> the ability to run Microsoft Word in addition to packet rewrites.
> Doing so skips several layers of abstraction, which is why they are
> On Fri, 16 Feb
> 2001, Nimesh Vakharia wrote:
> > > I doubt that the packet rewrites are taking place in ASIC - anytime you go
> > > above layer 2 doing dynamic stuff you've got to have a processor and ram.
> > >
> > Possible, this is what our sales/SE guys implied (its all
> > ASIC)... its quite possible it was a sales gimmick...
> > Nimesh.
> -------------- -- ---- ---- --- - - - - - -- - - - - - -
> Tony Bourke tonyIZZATvegan.net
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